Advances in semiconductor manufacturing processes, digital system architecture, and wireless infrastructure, among other things, have resulted in a vast array of electronic products, particularly consumer products, that drive demand for ever-increasing performance and density in non-volatile memory. As with many aspects of the semiconductor industry, there is a continuing desire and effort to achieve higher device packing densities and to increase the number of memory cells on a single die, wafer, or semiconductor device. At the same time, increased device speed and performance are also desired.
Common non-volatile memory devices include a virtual ground memory array composed of many individual memory cells, each capable of storing one or more bits of data. Typical non-volatile memory architectures include a memory array comprised of individual charge storing transistor cells, typically of a floating-gate type transistor or a charge trapping layer transistor. In common array architectures, the memory cells are typically arranged in a grid of rows and columns. Traditionally, each transistor memory cell includes a gate, a source and a drain node. In some non-volatile memory, each memory cell in a row shares a common wordline connected to the gate of each cell. The array also includes a number of bitlines typically provided perpendicular to the wordline. Each bitline connects to a source/drain node of each memory cell of a column in the array, where neighboring cells share a bitline.
In many non-volatile memory devices, the memory array is organized into individually addressable units, groups or sectors, which are accessed for read, write and erase operations through address decoding circuitry. The non-volatile memory device usually includes appropriate decoding and group selection circuitry, and driver circuitry for providing appropriate voltages to the wordlines and bitlines of the cells being operated upon, as is well known in the art.
Some non-volatile memory, such as flash memory, are generally programed by hot electron injection and erased by Fowler-Nordheim tunneling. These mechanisms are typically performed by applying appropriate voltages to the gate, source and drain nodes of the targeted memory cell. During an erase or write operation, appropriate voltages are applied to the transistor nodes to cause charge to be removed from or stored onto the floating gate or the charge trapping layer of the targeted transistor cell. During a read operation, appropriate voltages are applied to the transistor nodes to cause a current to flow in the targeted cell, wherein the amount of such current is indicative of the value of the data stored in the cell. The memory device includes appropriate circuitry to sense the resulting cell current in order to determine the data stored therein, which is then provided to data bus terminals of the device for access by other devices in a system in which the memory device is employed.
The location of a targeted memory cell is identified according to the row and column of its position in the memory array. Peripheral circuitry receives addressing information and decoding circuitry is used to select the appropriate wordline and bitlines associated with the target cell.
To initiate a write operation at the target cell, a programming voltage is applied to the appropriate wordline coupled to the gate of the targeted transistor memory cell. Generally, only a bitline corresponding to a drain node of the selected target cell receives a drain bias program voltage, while the other bitline corresponding to the source node of the target cell receives a source bias voltage at or near ground potential. During the write operation, known circuits electrically decouple all other bitlines of neighboring nontargeted cells from a voltage source such that the bitlines are said to be “floating”. Because the neighboring bitlines are floating, the neighboring memory cells in the same row ideally do not conduct a current and are not affected by the write operation at the target cell. However, the neighboring cells in the same row are in a resistive state due to the voltage applied at their gates by virtue of being connected to the same wordline as the target cell. Moreover, due to capacitive coupling between metal bitlines, a reverse potential difference can occur between the drain and source nodes of the neighbor cell resulting in an undesired write disturb on the untargeted neighbor cell. A write disturb is an unfortunate by-product of a high voltage applied to a bitline to change the state of a target memory cell.
In some memory arrays, capacitive coupling between a target bitline and a neighboring floating bitline as well as a bitline to bitline leakage current between the two, effectively “pull up” the voltage potential experienced on the neighboring “floating” bitline during a write operation to closely follow the drain bias voltage applied at the target cell bitline. Accordingly, any potential difference between the source and the drain nodes at the untargeted cell is a small value and thus the minimal current through the untargeted cell typically does not result in a severe write disturb condition at the untargeted cell. Additionally, some non-volatile memory devices control a ramp rate of the target bitline to enable a more effective “pull up” of the voltage potential at the floating bitline so that the potential difference between a target cell bitline and the neighboring floating bitline is reduced. This technique, however, is less effective in higher density memory arrays that have been demanded by the market.
Some non-volatile memory devices achieve higher density virtual ground memory arrays by reducing the physical dimensions of each of the transistor memory cells and adding more rows of cells to the array. Accordingly, the bitlines coupled to the source/drain nodes of the memory cells are positioned physically closer together and each bitline has an increased resistive value due to increased load and length. Thus, bitlines in higher density arrays exhibit an increased RC time constant which induces a delay in charging up the floating neighboring bitline. Due to this delay, the floating bitline voltage charges more slowly and does not closely follow the target bitline voltage during a write operation. Thus, an increased potential difference experienced between the source and drain nodes of the neighboring memory cell potentially causes a write condition at the untargeted neighboring cell resulting in severe and undesired write disturb effects. Moreover, transistors with smaller physical dimensions are more sensitive, thus even previously tolerated write conditions in the neighbor cell may result over time in severe disturbance to the charge and therefore data of the neighbor cell. Thus, as higher density and smaller die size structures are implemented in non-volatile memory devices, the write disturb problem becomes more severe and harder to handle.
What is needed is an apparatus and method for enabling write operations for a high density memory array at desirable performance speeds, while preserving the existing state of neighboring cells.
It is noted that the cross-sectional representations of various semiconductor structures shown in the figures are not necessarily drawn to scale, but rather, as is the practice in this field, drawn to promote a clear understanding of the structures, process steps, and operations which they are illustrating.